RACE: A Centralized Platform Computer Based Architecture for Automotive Applications

Sommer, Stephan; Camek, Alexander; Becker, Klaus; Buckl, Christian; Zirkler, Andreas; Fiege, Ludger; Armbruster, Michael; Spiegelberg, Gernot; Knoll, Alois · 2013 · OpenAlex-citations

DOI: 10.1109/ievc.2013.6681152

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Summary

The paper addresses the escalating complexity of automotive software architectures driven by the proliferation of advanced driver assistance systems (ADAS), autonomous driving functions, and increased software volume. Current distributed architectures, such as AUTOSAR, struggle to manage the integration, verification, and fail-operational requirements of these new functionalities. Motivated by the need for a scalable, safe, and flexible platform, the authors propose RACE (Centralized Platform Computer), an architecture inspired by Integrated Modular Avionics (IMA) concepts from the aerospace industry. The goal is to replace domain-specific Electronic Control Units (ECUs) with a centralized computing platform that supports zero accidents, Plug&Play functionality, and always-on connectivity. The RACE architecture consists of a Centralized Platform Computer (CPC) comprising redundant Vehicle Control Computers (VCCs) and smart sensors/actuators connected via a high-bandwidth Ethernet backbone. The hardware design utilizes a duo-duplex Ethernet ring topology to ensure fail-operational behavior, providing redundant data paths without requiring parallel physical networks. The system distinguishes between duplex control computers (DCCs) for fail-safe critical tasks and simplex control computers (SCCs) for non-critical functions. The software layer employs a middleware-based Runtime Environment (RTE) that uses a publish-subscribe communication pattern to decouple applications from hardware infrastructure. Applications are modeled using "Manifests" that define data topics, timing constraints, and safety integrity levels, enabling automated deployment and verification. Key findings highlight the effectiveness of the proposed middleware and network design in managing mixed-criticality systems. The Ethernet ring topology, utilizing BroadR-Reach technology, supports two traffic classes: cyclic, safety-critical data with guaranteed latency and redundancy, and acyclic bulk data for infotainment and updates. The RTE provides time and space partitioning, allowing applications with different Automotive Safety Integrity Level (ASIL) classifications to run on the same hardware safely. The architecture enables deterministic execution and simplifies the integration of new software components without replacing the entire system, contrasting with the rigid deployment models of AUTOSAR and ARINC 653. The significance of this work lies in demonstrating a viable path toward centralized automotive computing that meets stringent safety standards like ISO 26262 ASIL-D. By leveraging standardized Ethernet technologies and a flexible middleware layer, RACE reduces development costs and complexity while supporting future-proof features like autonomous driving. The paper concludes that this approach offers superior configurability and safety mechanisms compared to existing automotive standards, with plans to validate the architecture in a prototypical electric vehicle.

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