Resource Efficient Hardware Implementation for Real-Time Traffic Sign Recognition

Weng, Huai-Mao; Chiu, Ching-Te · 2018 · OpenAlex-citations

DOI: 10.1109/icassp.2018.8462298

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Summary

This paper addresses the challenge of implementing real-time Traffic Sign Recognition (TSR) for Advanced Driver Assistance Systems (ADAS) with high resource efficiency. While machine learning methods offer high recognition rates, they often suffer from excessive computational complexity, whereas traditional image-processing methods are fast but less accurate. To balance speed and accuracy, the authors propose a hybrid TSR method divided into detection and recognition stages, optimized for hardware implementation to meet real-time processing requirements while minimizing power consumption and chip area. The proposed method utilizes a two-stage pipeline. In the detection stage, the system employs a modified Normalized RGB (NRB) color transform to segment red and blue colors, followed by a novel Single-Pass Connected Component Labeling (CCL) algorithm. This CCL variant eliminates the traditional "merge-stack" operations by recording connected relations during the scan phase and updating labels iteratively, significantly reducing memory usage and computation time. In the recognition stage, the Histogram of Oriented Gradient (HOG) descriptor is generated using simplified fixed-point arithmetic and approximate formulas for gradient magnitude and orientation. These descriptors are then classified using a Support Vector Machine (SVM). The system was evaluated using the German Traffic Sign Detection Benchmark (GTSDB) dataset, which contains 1360 × 800 pixel images. Experimental results demonstrate that the method achieves a 96.61% detection rate and a 90.85% recognition rate. The authors optimized the HOG module by reducing input data to 4-bit width and output descriptors to 3-bit width without significant loss in accuracy. The hardware implementation, designed using TSMC 90 nm technology, integrates the detection and HOG modules in hardware while handling SVM classification in software. This design operates at a 105 MHz clock rate, processing images at 135 frames per second. The chip occupies approximately 1 mm² and consumes close to 8 mW of power. Compared to advanced existing designs, the proposed CCL storage size is reduced by 20%. The significance of this work lies in its demonstration that TSR can be performed in real-time with minimal hardware resources. By simplifying complex algorithms like CCL and HOG for ASIC implementation, the authors provide a cost-effective and energy-efficient solution for automotive safety systems. The study confirms that hybrid methods, when carefully optimized for hardware constraints, can achieve high accuracy and speed simultaneously, making them viable for deployment in modern vehicles where processing power and energy budgets are limited.

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• sign visibility legibility